1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a silicide layer on the surface of a gate electrode or the surface of a source or drain diffusion layer of an insulating gate type field effect transistor (a MOS transistor).
2. Description of the Related Art
The development of a semiconductor device with a fine pattern size and a high density is still carried dynamically. At present, very highly integrated semiconductor devices such as a memory device and a logic device have been developed based on the design rule of 0.15 to 0.25 .mu.m. With the high integration of the semiconductor device, it becomes very important to reduce the gate electrode width and diffusion layer width and to reduce the film thickness of each of the components of the semiconductor device.
When a diffusion layer is formed to have a shallow junction, a parasitic resistance of the MOS transistor increases to decrease the drive capability of the MOS transistor. Also, the reduction of the wiring width or film thickness of the gate electrode necessarily increase the wiring resistance to largely influence to the delay of the circuit operation.
Therefore, in the semiconductor device with fine patterns, the technique to form high melting point or refractory metal silicide on the surface of the diffusion layer or the surface of the gate electrode becomes important. Especially, in the silicide layer forming technique or the salicide layer forming technique, high melting point metals such as cobalt becomes essential to the MOS transistor with fine patterns. In this case, because it is difficult to keep the resistance value of the silicide layer constant, various methods are studied and proposed. For example, in case of the formation of a silicide layer of cobalt, it is especially difficult to control the heat reaction of cobalt with silicon.
A conventional method of forming a silicide layer of cobalt is described in Japanese Laid Open Patent Application (JP-A-Heisei 2-45923: hereinafter, to be referred to as a first conventional example). Or, the method described in Japanese Laid Open Patent Application (JP-A-Heisei 7-86559: hereinafter, to be referred to as a second conventional example) is known.
The first conventional example will be described with reference to FIGS. 1A to 1C. FIGS. 1A to 1C show the salicide forming process of cobalt.
As shown in FIG. 1A, an N well 102 is formed in a P-type silicon substrate 101 by a well known method. Subsequently, a field oxide film 103 is formed on the surface of the P-type silicon substrate 101 by a selective oxidation method. A gate oxide film 104 such as a silicon oxide film and a polysilicon film are formed in order in an active region which is surrounded by the field oxide film 103. Phosphorus ions as impurities are doped in the polysilicon film by a well known technique. Thus, the resistance value of the polysilicon film is reduced.
Next, the above-mentioned polysilicon film is patterned by a well known photolithography method and the dry etching method so that a gate electrode 105 is formed. Then, an N-type impurity diffusion layer 107 with a low concentration and a P-type impurity diffusion layer 108 with a low concentration are formed by the photolithography method and the ion implantation method. Subsequently, side wall spacers 106 composed of a silicon oxide film or a silicon nitride film are formed on the side walls of the gate electrode 105 using a well known chemical vapor deposition (CVD) method and the dry etching method.
Next, as shown in FIG. 1B, a P-type impurity diffusion layer with a high concentration and an N-type impurity diffusion layer with a high concentration are formed by the photolithography method and the ion implantation method. Thus, the N-type source and drain diffusion layers 109 and the P-type source and drain diffusion layers 110 are formed to have a LDD (Lightly Doped Drain) structure. Subsequently, native oxide films (not shown) on the surface of the polysilicon film as the gate electrode and on the surface of the silicon substrate are removed and a cobalt film 111 is sputtered without heating the silicon substrate. Then, the silicon substrate is heated to the temperature at which a CoSi.sub.2 film 112 is formed, in a vacuum apparatus without exposing the surface of the silicon substrate to the atmosphere. In this case, the heating temperature is in a range from 500.degree. C. to 800.degree. C.
Next, as shown in FIG. 1C, a wet etching is performed by the mixture solution of a sulfuric acid solution and a hydrogen peroxide solution to selectively remove non-reacting portions of the cobalt film 111 which exist on the field oxide film 103 and the side wall spacers 106. Thus, the CoSi.sub.2 film 112 is selectively formed on the surface of the gate electrode 105, on the surfaces of the N-type source and drain diffusion layers 109 and on the surfaces of the P-type source and drain diffusion layers 110 of the MOS transistor without forming any cobalt silicide layer on the surfaces of the insulating films, i.e., the field oxide film 103 and the side wall spacers 106.
Next, the second conventional example will be described with reference to FIGS. 2A to 2C. FIGS. 2A to 2C shown the salicide forming process using a metal film such as a cobalt film.
As shown in FIG. 2A, an element separation region 202 is formed on the surface of a silicon substrate 201. Subsequently, a gate oxide film 203 such as a silicon oxide film and a polysilicon film is grown in order in the active region which is surrounded by the element separation region 202. Then, phosphorus ions as impurities are doped in the polysilicon film by the known technique. Thus, the resistance value of the polysilicon film is reduced. Subsequently, the above-mentioned polysilicon film is patterned by a well known photolithography method and the dry etching method such that a polysilicon gate 204 is formed. Subsequently, side wall spacers 205 are formed on the side walls of the polysilicon gate 204 by a well known method.
Next, a cobalt film 206 and a titanium film 207 are continuously deposited on the whole surface by a sputtering method. In this case, the film thickness of each of the metal films is set to about 10 nm. Subsequently, a heat treatment like a rapid thermal annealing (RTA) method is performed at about 700.degree. C. in the nitrogen ambience. Thus, as shown in FIG. 2B, a cobalt silicide film 208 is formed on the surface of the silicon substrate 201 and the surface of the polysilicon gate 204. At this time, the cobalt film 206 on the silicon oxide film of the element separation region 202 and the side wall spacers 205 is not silicided and remained in the non-silicided state. Also, the whole of titanium film 207 is changed into a titanium nitride film 209 through the above-mentioned heat treatment. Subsequently, a wet etching is selectively performed to the above-mentioned non-silicided cobalt film 206 and the titanium nitride film 209. Thus, as shown in FIG. 2C, a cobalt silicide film 208 is selectively formed in the gate, source and drain area of the MOS transistor formed on the silicon substrate 201.
However, in the above-mentioned first conventional example, the reaction of cobalt with silicon occurs to form a CoSi.sub.x film in the temperature at which a CoSi.sub.2 film is formed, on the insulating films such as the field oxide film 103 and the side wall spacers 106. When the CoSi.sub.x film is once formed in this way, it is difficult to remove the CoSi.sub.x film by a wet etching method. For example, when the CoSi.sub.x film formed on the insulating film is etched, using a mixture solution of a hydrochloric acid solution and a hydrogen peroxide solution, the CoSi.sub.2 film formed on the gate or diffusion layer is also etched. For this reason, the resistance values of the source and drain diffusion layers and gate electrode, specifically the sheet resistance values of them increase in the formation of a MOS transistor with fine patterns.
Also, the film thickness control of the cobalt silicide layer formed thus is difficult. As a result, it is difficult to decrease the deviation of sheet resistance values of the gate electrodes and source and drain diffusion layers of the MOS transistors in a semiconductor chip or a semiconductor wafer where the semiconductor device is formed. For this reason, the deviation of characteristics of the MOS transistors increases.
Also, in the above-mentioned second conventional example, the cobalt film 206 and the titanium film 207 are deposited by the sputtering method. Depending on the condition of the heat treatment, there is a case that a mixed crystal silicide film of cobalt and titanium is formed through the heat reaction of the cobalt film and the titanium film. As a result, the number of silicide processes increases and the manufacturing process become complicated.
Also, in this case, it is also difficult to control the film thickness of the cobalt silicide layer. For this reason, as described above, the deviation of characteristics of the MOS transistor in the semiconductor chip or the semiconductor wafer increases.
With the miniaturization and high integration of the MOS transistors, the minimum pattern size of the gate electrode and source and drain diffusion layers becomes equal to or less than 0.5 .mu.m. In this case, the sheet resistance value of the gate electrode or diffusion layer becomes high, compared with the sheet resistance value of the CoSi.sub.2 film when the gate electrode width or the diffusion layer width is wide. That is, the resistance value of the completed silicide layer has the pattern size dependency. As a result, the design of the MOS transistor or the semiconductor device becomes difficult.